Sony Manufacturing Process Of A Cmos Image Sensor Detailed At Iedm 2017

Sony manufacturing process of a CMOS image sensor detailed at IEDM 2017

The Sony group (Sony Semiconductor Solutions Corp and Sony Semiconductor Manufacturing Corp) made an announcement about the manufacturing process of a CMOS image sensor that is made by stacking layers including a DRAM layer and making them into a chip at IEDM 2017.

The image sensor was first announced at ISSCC 2017 and has already been employed for smartphones (See related article). But this is the first time that the group has unveiled the manufacturing process.

Image sensors designed for highly-functional smartphones usually have a two-layered structure consisting of (1) a backside-illumination imaging part (upper layer) and (2) logic circuit part (lower layer). This time, the Sony group inserted a DRAM layer between the imaging part and the logic circuit part, forming a three-layered structure. In other words, from the top, the layers are the imaging part, DRAM and logic circuit part.

The image sensor having the DRAM layer (source: Sony)[Click to enlarge image]

The DRAM layer enables to shoot images at a very fast speed. For example, the image sensor announced at ISSCC 2017 was capable of shooting 1,920 x 1,080-pixel video at a frame rate of 960fps.

The image sensor having the DRAM layer (top). It can shoot images of a fast-moving object without distortion. On the other hand, a conventional image sensor causes distortion when taking images of a fast-moving object.[Click to enlarge image]

DRAM thickness reduced to 3 micrometers

The overview of the manufacturing process[Click to enlarge image]

The overview of the manufacturing process of the DRAM-embedded chip is as follows. First, the imaging part, DRAM and logic circuit are formed on different silicon (Si) wafers, respectively. The imaging part, DRAM and logic circuit are made by using 90nm, 30nm and 40nm manufacturing processes, respectively.

Second, the DRAM wafer and the logic circuit wafer are joined together, and the thickness of the DRAM wafer is reduced to 3μm, which is less than 1/200 of the original thickness.

Third, the DRAM and logic circuit are electrically connected by using TSVs (through silicon vias). Fourth, the wafers of the DRAM and logic circuit are joined to the wafer of the imaging part. Lastly, it is thinned down and connected by using TSVs, forming a three-layered structure.

The thickness of the DRAM is reduced to 3μm so that the thickness of the new (three-layered) chip becomes equivalent to that of the two-layered chip consisting of the imaging part and logic circuit. The thickness of the new chip is 130μm.

About 35,000 TSVs used
The Sony group reduced the area of the I/O (input/output) part by narrowing the pitch of TSVs. In addition, the capacity of the I/O part was reduced, contributing to lowering power consumption. The numbers of TSVs connecting the imaging part and DRAM and TSVs connecting the DRAM and logic circuit are about 15,000 and about 20,000, respectively. Both of the TSVs have a diameter of 2.5μm and a pitch of 6.3μm.

At the IEDM, the Sony group disclosed the results of several reliability tests conducted by using an evaluation chip of the DRAM-embedded image sensor and stressed that there is no problem.

The size of the imaging part is 1/2.3 inch, and its pixel count is 21.2 million (5,520 x 3,840). The image sensor shoots 4:3 and 16:9 images with 19.3 million pixels and 17.1 million pixels, respectively. The pixel size is 1.22μm, and the capacity of the DRAM is 1 Gbit.