Sony's Image Sensor Enables Smartphone To Take 960fps Video


Sony's Image Sensor Enables Smartphone to Take 960fps Video The Sony group developed a CMOS image sensor chip by stacking layers including a DRAM layer and announced it at ISSCC 2017 (lecture number: 4.6).
The group (Sony Semiconductor Solutions Corp, Sony Semiconductor Manufacturing Corp and Sony LSI Design Inc) expects that the chip will be used for mobile devices such as smartphones.


In general, image sensors designed for highly-functional smartphones have a two-layered structure that uses a backside-illuminated image sensing part for the upper part and a logic circuit part for the lower part. This time, the group added a DRAM layer between the image sensing part and the logic circuit part to form a three-layered structure.

With the DRAM layer, it became possible to take images at a very high speed. For example, it is possible to take 19.3-Mpixel still images at a frame rate of 120fps and video with a pixel count of 1,920 x 1,080 at 960fps.

Without DRAM, the reading speed is determined by the data transmission speed of the interface (I/F) circuit that outputs image data to external DRAM. When DRAM is added to a chip, a large amount of data output from the logic circuit can be temporarily stored in the DRAM before it is transmitted to the I/F circuit. As a result, the reading speed is hardly affected by the transmission speed of the I/F circuit.

The Sony group has already developed a two-layered backside-illuminated image sensor whose back side is integrated with a DRAM die. And it has already been employed for digital cameras (See related article). The group considers the newly-developed sensor as a product for mobile devices for which smaller sensors are highly demanded.

The size and pixel count of the CMOS image sensor is 1/2.3 inch and 21.2 million (5,520 x 3,840), respectively. With an aspect ratio of 4:3 and 16:9, 19.3- and 1.71-Mpixel images are taken, respectively. The size of each pixel is 1.22μm.

The I/F circuit supports MIPI D-PHY (2.2Gbps per lane) or MIPI C-PHY (2.0Gsps (sample per second) per lane). When 4k video is being taken at a frame rate of 30fps, the power consumption of the sensor is 424mW. Its dynamic range is 64.8dB.

The new sensor transmits the output from the light-receiving part (PD: photo diodes) to a four-level AD (analog-to-digital) converter, digitizes it and outputs it to a "pre-processor." The pre-processor performs preprocesses such as bit formation and stores it in the DRAM via a bus.

The "main processor" connected to the bus carries out simple processes including defect correction. And the results are output to the I/F circuit via the bus.

The transmission rate of the bus is 102Gbps (512 bits, 200MHz). The capacity of the DRAM is 1 Gbit (128 bits, 200MHz x 4 channels).

The image sensing part, DRAM and logic circuit part were manufactured using 90nm (1AL5Cu), 30nm (3AL1W) and 40nm (1AL6Cu) process technologies, respectively. The logic circuit part is equipped with the AD converter, pre-processor, main processor, I/F circuit, etc.

The configuration of the image sensing part is "1P4T," which uses four transistors for transmission, amplification, selection and reset, respectively, per photo diode. The transistor for transmission is formed for each pixel while the other three kinds of transistors are shared by eight pixels. This is a commonly-used configuration for applying advanced process technologies to image sensors, according to the Sony group.